1. Field of the Invention
This invention relates to computers and more particularly to addressing of computer memories.
2. Description of the Related Art
Many computer system architectures have inherent limits on the size of memory available to the system. For example, in '186 processors, i.e., processors compatible with the 80186 processor, the address range is limited to 1 Mbyte. The Motorola HS68000 processor is limited to 16 Mbytes. In order to extend the address range beyond those limitations, address banking provides one solution for interfacing with devices such as SRAM, Flash memory, and ROM, which do not have multiplexed address buses. For such memory devices, banking schemes utilize one or more address bits which are set external to the processor's normal addressing calculation. One way to provide these extra address bits would be to use the programmable input/output (PIOs) of the AM186.TM.ES. Because these bits are programmable, they can be written to the appropriate value to provide entry to or exit from a memory bank.
One example of a banking technique for use with devices with non-multiplexed addresses, is shown in FIG. 1. AM186.TM.ES processor 107, with an address range of 1 Mbyte, could utilize PIO bits 20-23 to expand the 1 Mbyte address range of the '186 to 2.5 Mbytes.
In more detail, in the exemplary system shown in FIG. 1, the upper memory chip select (UCS), is mapped to the upper 256 Kbytes of the 1 Mbyte address space and provides access to the flash memory 101 (which may be, e.g., AM29F010 flash memory) containing 256 Kbytes (128K.times.8).times.2). The lower memory chip select (LCS), is mapped to the lower 256 Kbytes, and provides access to memory 103. The middle chip select (MCS0) is mapped to 256 Kbytes of address space and is used to address flash memory 105. Thus, memory banking is provided in the address space of block 203. The PIO bits are used to select one of 16 independent Flash segments of 256 Kbytes each in flash memory 105. Thus, the system in FIG. 1 provides a total of 2.5 Mbytes of address space and provides expanded memory capability without any glue logic, i.e., logic between the processor and the memory providing e.g., address decoding.
However, the above scheme will not work for Dynamic Random Access Memories (DRAMs) because DRAMS require multiplexing the address into row and column addresses. That is, DRAMs require that the address be split into rows and columns with the row address being provided to the DRAM during a first time period (row access strobe (RAS) cycle) and the column addresses being provided to the DRAM during a second time period (column access strobe (CAS) cycle). Multiplexing the row and column addresses reduces the number of address pins required on a DRAM and enables, e.g., a twenty bit address to be provided to a DRAM with only 10 address pins. However, it makes the banking schemes previously discussed unsuitable because of the need to incorporate the banked address into the multiplexed address. It would be desirable to provide expanded memory capability for DRAMs where multiplexed addresses are required. Further, it would be desirable to provide a glueless (no peripheral logic required) interface that provides DRAM banking capability. Thus, it would be desirable to find a way to multiplex in extra address bits to provide banking capability for DRAMs, i.e., increased address capability.